1. Field of the Invention
The present invention relates to an intermediate structure of a semiconductor device and a method of manufacturing the same.
2. Description of the Related Art
BGA (Ball Grid Array) type semiconductor devices have been manufactured by using a MAP (Mold Array Process), in which a wiring board having a plurality of product formation portions is prepared, a semiconductor chip is mounted on each of the product formation portions, a sealing body is formed to integrally cover the plurality of product formation portions on the wiring board, and the wiring board is divided into the individual product formation portions.
However, such a semiconductor device has a problem that a wiring board is susceptible to warpage due to the fact that sealing resin is caused to shrink more than the wiring board due to cure shrinkage of the sealing resin.
The problem of warpage of the wiring board is also caused by the fact that the sealing body is formed by injecting a sealing resin through a gate during a transfer molding process, resulting in uneven distribution of filler (spherical glass members).
Furthermore, according to the related art, a plurality of gates are provided in a central part of the cavity for injecting the sealing resin through the gates. Therefore, in the same manner as described above, distribution of the filler will differ between the central part where the gates are provided and the opposite end parts of the cavity, when viewed in plan view. For example, there may be more filler in the opposite end parts of the cavity than in the central part where the gates are provided. This uneven distribution of the filler in the sealing body also leads to warpage of the wiring board.
If the warpage occurs in the wiring board, as described in the above, it may lead to deteriorated transportability of the wiring board or lowered positioning precision of the wiring board. Furthermore, the deteriorated transportability of the wiring board may cause deterioration in manufacturing efficiency, and the lowered positioning precision may cause deterioration in ball mounting accuracy or board cutting accuracy, possibly resulting in generation of defectives.
Moreover, warpage may occur also in a semiconductor device which has been assembled by the method as described above.
A semiconductor device of an MCP (Multi Chip Package) type or the like has a plurality of semiconductor chips mounted in layers, which increases the thickness of the sealing resin as well. The increased thickness of the sealing body makes more serious the problem of the warpage caused by the cure shrinkage of the sealing resin or uneven distribution of the filler.
Japanese Laid-Open Patent Publication Nos. 2001-44229 and 2001-44324 disclose a technology to reduce the warpage of a wiring board by forming a sealing body, divided into sections, so as to collectively cover a plurality of product formation portions.
However, although the formation of the divided sections of the sealing body on the wiring board alleviates the warpage of the wiring board to some extent, warpage will occur in each part of the wiring board corresponding to each section of the sealing body.
Furthermore, in a recent trend, the size of a wiring board has been increased to increase the number of products obtainable from a wiring board, and hence the size of a sealing body has also been increased. As a result, the problem of warpage has become even more serious.
If the sealing body is divided into a greater number of sections for the purpose of reducing the warpage, the wiring board will come into contact with molding dies over a greater area, resulting in reduced number of products obtainable from the wiring board.
For example, Japanese Laid-Open Patent Publication No. H10-326800 discloses a technology in which a sealing resin is formed on a wiring board which is in a warped state, so that the warpage is reduced caused by the difference in heat shrinkage between the wiring board and the sealing resin.
For example, Japanese Laid-Open Patent Publication No. 2007-281374 discloses a technology in which there is provided, between each chip and external terminal on a wiring board, a local deformation member having a different coefficient of thermal expansion from that of the wiring board, so that the local deformation member is deformed in an opposite direction from the warpage occurring in the chip mounting region.